1. Field of the Invention
The present invention relates generally to photon detection, and more particularly to detector amplifiers for single photon read-out of semiconductor photodetectors in pixellated imaging arrays.
2. Description of the Related Art
Optical sensors transform incident radiant signals in the X-ray (xcex less than 0.001 xcexcm), ultraviolet (xcex=0.001-0.4 xcexcm), visible (xcex=0.4-0.8 xcexcm), near infrared (IR) (xcex=0.8-2 xcexcm), shortwave IR (xcex=2.0-2.5 xcexcm), mid IR (xcex=2.5-5 xcexcm), and long IR (xcex=5-20 xcexcm) bands into electrical signals that are used for data collection, processing, storage and display, such as real-time video. Available conventional photodetectors such as photodiodes and photoconductors are inexpensive, exhibit bandwidths that support current video frame rates, are sensitive to wavelengths well into the long IR band, and exhibit a high degree of uniformity from pixel to pixel when used in an imaging array. However, these photodetectors have no gain, i.e. each incident photon generates, at most, a single electron. Thus, these imaging systems work well only in moderate to bright light conditions. At low light levels, they provide electrical signals that are too small to be read-out by conventional readout circuits.
In conditions of low ambient light, the standard photodetector is often replaced with an avalanche photodiode that provides significant gain such that conventional read-out circuits, such as charge coupled devices, i.e. CCDs, can read out the amplified signal at video frame rates with a high signal-to-noise ratio (SNR). The fabrication of avalanche photodiodes is much more difficult and expensive than standard photodetectors because they must simultaneously exhibit very high controlled gain and very low noise. Furthermore, currently available avalanche photodiodes exhibit relatively poor uniformity, are constrained to shorter wavelengths than standard photodetectors (0.7 xcexcm), and have limited sensitivity due to their relatively low quantum efficiency. Imaging intensified systems use an array of avalanche photodiodes or micro-channel plates to drive respective display elements such as CCDs or phosphors, and have even lower wavelength capabilities (approximately 0.6 xcexcm max) due to the limitations of the photodiode.
Chamberlain et al. xe2x80x9cA Novel Wide Dynamic Range Silicon photodetector and Linear Imaging Arrayxe2x80x9d IEEE Transactions on Electron Devices, Vol. ED-31, No. 2, February 1984, pp. 175-182, herein incorporated by reference, describes a gate modulation technique for single photon read-out of standard photodetectors with wide dynamic range. Chamberlain provides a high-gain current mirror that includes a load FET (Field Effect Transistor) whose gate is connected to its drain to ensure sub-threshold operation. The signal from the photodetector is injected into the load FET thereby producing a signal voltage at the gate of a gain FET with high transconductance. This signal modulates the gain FET""s gate voltage, which is read out and reset via a FET switch. The key benefit of this approach is that a detecting dynamic range of more than 107 for each detector in the array is produced. Unfortunately, the circuit is highly sensitive to variations in the threshold voltage of the various transistors. The pixel-to-pixel VT non-uniformity associated with standard silicon CMOS fabrication processes degrades the instantaneous dynamic range of the imaging array even as the circuit""s logarithmic characteristic enhances each pixel""s ability to operate over a much larger total dynamic range.
Although this specific gain modulation technique is useful for detecting signals across a broad spectral range, the front-end bandwidth severely restricts the imaging array""s bandwidth. Specifically, the dominant RC time constant is the parallel combination of the photodetector""s capacitance and the resistance of the load FET. In sub-threshold operation, the FETs transconductance is very low and, hence, its load resistance is very large, at xe2x89xa71015 ohms; the minimum resulting RC time constant is on the order of tens of seconds. Chamberlain""s gate modulation technique is thus only practically useful for imaging daylight scenes or static low-light-level scenes such as stars. Furthermore, to achieve large current gain, the load FET is typically quite small. As a result, the load FET exhibits substantial 1/f noise, which under low light conditions seriously degrades the performance of the imaging array.
U.S. Pat. No. 5,933,190 discloses a circuit having a first reading transistor 23 in series with the load transistor of Chamberlain to read-out the voltage across the load transistor rather than the other leg of the current mirror. While this configuration self-biases the detectors in the imaging array, and the usable dynamic range for each pixel is still at least 107, the time constant is unchanged relative to Chamberlain""s teaching. Further, the instantaneous dynamic range at a specific irradiance across an imaging array having pixels of such design is still highly sensitive to the threshold uniformity from transistor to transistor. The pixel-to-pixel VT non-uniformity associated with standard silicon CMOS fabrication processes degrades the instantaneous dynamic range of the imaging array even as the circuit""s logarithmic characteristic enhances each pixel""s ability to operate over a much larger total dynamic range. Though the ""190 reference also teaches a method for reducing the non-uniformity by degrading the various transistors by applying a stressing over-voltage, this is definitely not a recommended procedure for a high-quality, long-life camera system.
U.S. Pat. No. 5,929,434 teaches an alternative current mirror configuration that suppresses the impact of the VT non-uniformity via an alternative current mirror configuration that also reads the integrated current after an integration period rather than the instantaneous voltage. The preferred embodiment minimizes, to first order, the variations in threshold non-uniformity by subtracting the non-uniformity within each pixel. Unfortunately, the residual pixel-to-pixel variations still dominate the imager""s fixed pattern noise irrespective of background flux, depending on the MOS fabrication technology. The magnitude of pattern noise can often be larger than the signal, so off-chip compensation of pixel-to-pixel non-uniformity is required.
The negative feedback amplifier, 16, disclosed in U.S. Pat. No. 5,929,434, significantly reduces the input impedance of the high-gain circuit and thereby enhances its bandwidth. In the case where the buffer amplifier is approximated to have infinite voltage gain and finite transconductance, the dominant pole is given by:       τ          B      -      L        =            C      f              g              m        Q1            
where Cf is the effective feedback capacitance of the buffer amplifier from its output to its input. Assuming a cascoded amplifier configuration, the gate-source capacitance of Q1 (FET 74) is dominant and Cf is set by the gate-to-source capacitance of the sub-threshold Q1 (FET 74). This is approximately given by the parasitic metal overlap capacitance. Assuming a minimum width transistor in 0.25 xcexcm CMOS technology, for example, the minimum Cf will be approximately 0.2 fF for transistors having minimum width. The resulting time constant is on the order of tenths of a second. Though this facilitates single photon sensing at roughly video frame rates, additional improvements are needed to truly support single-photon imaging at frame rates higher than typically used for standard video.
U.S. Pat. No. 5,665,959 teaches yet another approach consisting of a digitized system wherein each pixel uses a pair of cascaded inverters with a sub-threshold transistor at its front-end to generate extremely high transimpedance. Since the small photosignal at backgrounds on the order of one electron translates to extremely high input impedance, the photosignal is effectively integrated onto the Miller capacitance of a first-stage inverter prior to being further amplified by a second stage inverter. A resulting charge-to-voltage conversion gain  greater than 1 mV/exe2x88x92 is hence claimed. Nevertheless, the read noise of the charge-integrating first stage will limit the SNR for many practical cases since insufficient means are provided to band-limit the first amplifier""s wideband noise. The read noise for the first stage can be approximated as similar to that of a charge integrator such that:       N          stage_      ⁢      1        =            1      q        ⁢                            kTC          fb                ·                                            C              det                        +                          C              fb                                                          C              L                        +                                                            C                  fb                                ·                                  C                  det                                                                              C                  fb                                +                                  C                  det                                                                        
where k is Boltzmann""s constant, T is the temperature, Cfb is the parasitic feedback capacitance of the first stage, Cdet is the photodiode capacitance and CL is the load capacitance at the amplifier""s output. Assuming practical values consistent with the understanding of those skilled in the art, the detector capacitance is typically a minimum of 15 fF for the hybrid imager of the U.S. Pat. No. 5,665,959 preferred embodiment. Assuming a Miller capacitance for the first stage amplifier of 5 fF and a load capacitance of 350 fF (i.e., the storage capacitance Cstr1), then the minimum read noise for the first stage will be in the range of 6 to 7 exe2x88x92; this is on top of the kT/C noise generated by opening transistor switch Qsw1 to perform the offset compensation of the composite two-stage amplifier. This performance is very good, but does not facilitate photon counting. Further, while the clocking of the two-stage amplifier facilitates large reductions in amplifier non-uniformity, this invention does not suppress the threshold variations of the load resistor at the front end.
U.S. Pat. No. 6,069,376 teaches a pixel amplifier with a speed switch suitable for still camera applications. This apparatus provides high-bandwidth signal integration with downstream gain, but its sensitivity is limited by the generation of reset noise at the storage element. Also, no facility is provided for maximizing the signal""s dynamic range at the input to the amplifier.
In general, the present invention is a photodetector readout circuit, with extremely high sensitivity, capable of single-photon detection. A photodetector (preferably a photodiode) integrates a small-signal photocharge on the detector capacitance in response to incident photons, producing a photodetector output signal. A buffer amplifier is arranged to receive the photodetector output signal and to produce a buffered photodetector output signal. A coupling capacitor has a first terminal connected to the buffered output signal and a second terminal connected to a signal input of a signal amplifier. The coupling capacitor shifts a signal level at the input to the signal amplifier by an adjustable offset voltage. An electronic offset reset switch, connected to the coupling capacitor, allows resetting of the offset voltage, preferably just after reset of the photodiode to allow transient decay. The offset voltage is the reset noise (kTC) generated by resetting the detector capacitance.
To synchronize the start of image formation across a pixellated array, the reset is simultaneous across the entire array. Each pixel""s offset voltage is clamped across each pixel""s coupling capacitor by reading the specific detector""s voltage, while simultaneously clamping the coupling capacitor to a specified voltage. When sampling of the photodiode signal begins, the actual signal is read relative to the offset voltage stored across the coupling capacitor. This effects correlated double sampling of the photogenerated signal, and eliminates the correlated noise generated by resetting (discharging) the photodetector capacitance. The clamping voltage is an adjustable voltage that also sets the quiescent operating point of the video signal amplifier above the threshold voltage of an integrating gain stage having common gate configuration and noise bandwidth set by a reset integrator.
The common gate amplifier provides large, adjustable current gain to further amplify the low-noise signal and integrate the boosted signal in a dedicated integration capacitor. At the end of a specified integration time, the integrated signal is sampled onto a second capacitor to synchronize the end of signal integration. Snapshot image capture is thus provided with very low noise referred back to the photodetector. The invention thereby improves transimpedance and dynamic range relative to prior solutions.